Olivia Hsu
Stanford University
owhsu@stanford.edu
Bio
Olivia Hsu is a final year Computer Science PhD student at Stanford University advised by Professor Kunle Olukotun and Professor Fredrik Kjolstad. She plans to go on the academic job market this Fall 2024 in search of a tenure-track assistant professor position. Olivia’s PhD research has focused on compiling sparse applications to various accelerated architecture systems. Her goals are to both make performant, domain-specific hardware and software easy to use and build systems that inform the use of these domain-specific systems. Her broad research interests also include computer architecture, computer and programming systems, compilers, programming languages, and digital circuits/VLSI. She received a B.S. in Electrical Engineering and Computer Science from the University of California, Berkeley in 2019. Olivia is a 2019 NSF Graduate Research Fellow, and her research won a distinguished paper award at PLDI 2023. Her webpage can be found at https://cs.stanford.edu/~owhsu.
Areas of Research
- Computer Architecture
The Efficient Mapping of Sparse Applications to Accelerated Systems
Sparse applications, like sparse tensor algebra and other sparse array operations, have become increasingly popular as a way to improve storage and performance. They also have tremendous opportunities for hardware acceleration, however, accelerating sparse applications has a host of programmability and usability challenges. This poster presents approaches to solve these challenges through the automatic mapping from a high-level sparse programming model to accelerated computing systems. We first address the problem for the entire CPU-accelerator system, by introducing a compiler that maps host sub-computation to external functions (in both hardware and software). Then, we zoom in to the accelerator sub-system and demonstrate how to program these sparse accelerators from higher-level languages for improved usability. In this problem space, we show how to generate sparse accelerator code at the representation level of their compute and memory units. We also present ideas on how to configure sparse accelerators at the level of detailed sparse dataflows and filtering mechanisms through the Sparse Abstract Machine (SAM). Specifically, SAM is an intermediate representation and abstract machine model for targeting sparse tensor algebra to reconfigurable and fixed-function spatial dataflow accelerators. Not only do we develop a front-end compiler from high-level languages to SAM, but also show how SAM can be leveraged to develop new hardware for sparse tensor algebra. With the abstraction derived from SAM, we designed and fabricated the first coarse-grained reconfigurable array (CGRA) for both dense and sparse applications, which achieves up to 565x better energy-delay product (EDP) for sparse kernels when compared against sparse libraries running on CPUs.