Sabrina Neuman
Harvard University
sneuman@mit.edu
Bio
Sabrina M. Neuman is a postdoctoral NSF Computing Innovation Fellow at Harvard University. Her research interests are in computer architecture design informed by explicit environmental and domain-specific insights. She is particularly focused on robotics applications because of their heavy computational demands and potential to improve the well-being of individuals in society. She received her SB MEng and PhD from MIT.
Robomorphic Computing: A Design Methodology for Domain-Specific Accelerators Parameterized by Robot Morphology
Robomorphic Computing: A Design Methodology for Domain-Specific Accelerators Parameterized by Robot Morphology
Robotics applications have hard time constraints and heavy computational burdens that can greatly benefit from domain-specific hardware accelerators. For the latency-critical problem of robot motion planning and control there exists a performance gap of at least an order of magnitude between joint actuator response rates and state-of-the-art software solutions. Hardware acceleration can close this gap but it is essential to define automated hardware design flows to keep the design process agile as applications and robot platforms evolve. To address this challenge we introduce robomorphic computing: a methodology to transform robot morphology into a customized hardware accelerator morphology. We (i) present this design methodology using robot topology and structure to exploit parallelism and matrix sparsity patterns in accelerator hardware; (ii) use the methodology to generate a parameterized accelerator for the gradient of rigid body dynamics a key motion planning kernel; (iii) evaluate FPGA and synthesized ASIC implementations of this accelerator for an industrial manipulator; and (iv) describe how the design can be automatically customized for other robot models. Our FPGA accelerator achieves latency speedups of 8x and 86x over CPU and GPU for a single computation and maintains speedups of 1.9x to 2.9x including computation and I/O latency when performing multiple computations as a CPU coprocessor. ASIC synthesis indicates an additional 7.2x speedup for single computation latency. We describe how this principled approach generalizes to more complex robots such as quadrupeds and humanoids as well as to other robotics kernels. Building on this foundation our goal in future work is to design a general processor for motion planning and extend our approach to the remaining stages in the robotics computational pipeline from perception to actuation building up a full hardware to software system stack for a complete robotics processor.