Seah Kim
UC Berkeley
seah@berkeley.edu
Bio
Seah Kim is a Ph.D. candidate in the Electrical Engineering and Computer Sciences department at the University of California, Berkeley, specializing in Computer Architecture and Systems. She works in the Berkeley Architecture Research (BAR) group and is affiliated with the SLICE lab (formerly the ADEPT lab), advised by Sophia Shao and Borivoje Nikolic. Her research focuses on SoC integration, design methodology, accelerator resource management, and hardware-software co-design opportunities in multi-accelerator systems. Prior to UC Berkeley, she earned a B.S. in Electrical and Computer Engineering from Seoul National University. She has been awarded the IEEE Micro Top Pick in Computer Architecture (2023), the Best Paper Award (DAC 2021), and the Distinguished Artifact Award (ISCA 2023). Seah was selected as a 2024 Rising Star in EECS and a 2023 ML and Systems Rising Star.
Areas of Research
- Computer Architecture
Cross-Stack Methodologies for Scalable SoC Design and Accelerator Management
My research focuses on developing scalable and efficient architectures for heterogeneous SoCs to address the rising compute demands of modern applications. The shift towards specialized domain-specific accelerators has introduced complex challenges related to resource management, hardware design, and integration. My work tackles these challenges across various layers of the stack, from SoC design and system integration to resource management and scheduling. First, AuRORA, a scalable accelerator virtualization methodology for multi-core, many-accelerator systems, enables dynamic resource partitioning by disaggregating accelerators from the host CPU while preserving software semantics. This provides a flexible and efficient accelerator management for modern SoC design. Next, MoCA enables adaptive execution by managing shared memory resources and scheduling multi-tenant workloads in DNN accelerators for resource-constrained environments. I have also contributed to Gemmini, a full-system, open-source DNN accelerator framework that supports the exploration of DNN hardware. Another aspect of my research is application-hardware co-design, such as SuperNoVA, which focuses on co-designing algorithms and accelerators for large-scale SLAM. Beyond these contributions, my research interests extend to SoC design and agile design methodologies. A key example is a chip tape-out I led, which demonstrated the scalability and efficiency of my architectural designs in silicon. Through my research, I aim to contribute to more efficient, scalable, and versatile SoCs capable of meeting next-generation compute demands.