Shuhan Liu
Stanford University
shliu98@stanford.edu
Bio
Shuhan Liu is a final-year PhD candidate in Electrical Engineering at Stanford University, advised by Prof. H.-S. Philip Wong. She earned her Bachelor’s degree in Microelectronics from Peking University in 2020 and her Master’s degree in Electrical Engineering from Stanford in 2022. Her research interests lie in advanced memory technologies, monolithic 3D integration, and cross-layer co-design. Her first-author work has been featured at leading conferences, including IEDM’23, IEDM‘24 (2 papers), IEDM‘25 (2 papers), and VLSI’23, VLSI‘24, and SOSP workshop Big Mem’25. These contributions have attracted coverage from major technology outlets such as IEEE Spectrum. Her outstanding contributions have been recognized with several prestigious honors, including the 2024 IEEE Electron Devices Society PhD Fellowship and the 2024 IEEE Roger A. Haken Best Student Paper Award.
Areas of Research
- Materials and Devices
BRIDGE: Blended Retention-Indexed Diverse Gain cEll
BRIDGE (Blended Retention-Indexed Diverse Gain cEll) is a gain cell memory platform developed in my PhD research. The 2-transistor (2T) gain cell memory offers high density and CMOS integration compatibility. By introducing oxide semiconductor (OS) transistors with ultra-low leakage current (< 1e-17 A/μm), BRIDGE expands the design space to support retention times spanning microseconds to seconds. Diverse gain cell configurations (Si-Si, OS-OS, OS-Si) and OS FET device designs enable fine-grained control over retention, speed, density, and power consumption. Amp Cell, an innovative 3D-scalable gain cell, extends the spectrum further, connecting 2T gain cell with 1T1C DRAM. BRIDGE is demonstrated on fabricated N40 CMOS+X monolithic 3D integration chip and N5 PDK simulation at the array level. Hybrid gain cell (OS-Si) demonstrates 3x density compared to high-density (HD) SRAM. BRIDGE-sim, the array-level model, introduces critical device metrics that incorporate array-level effects, facilitating design-technology co-optimization. Furthermore, integrating gain cells with non-volatile memories (e.g., RRAM) unlocks synergistic system-level benefits from device-circuit-architecture co-design, embodying the “1+1>2” philosophy where diverse memory technologies collaboratively enhance system functionality through integration.